Comments (3)
sschriner
commented on July 3, 2024
To follow up with this: Adding Q0 register support is a subtask within the larger task of supporting vector, SIMD, and FP instructions in ARMv7 and Thumb2 (for both remill and anvill)
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sschriner
commented on July 3, 2024
So we need to support a few more registers for that than Q0. (I can comprise a complete list a bit later).
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2over12
commented on July 3, 2024
As a workaround for now I'm allowing parsing to continue when a function spec fails to parse #294
from anvill.
Related Issues (20)
- Assertion in LLVM hit in unit tests for `BrightenPointerOperations` pass HOT 1
- Missed pointer lifting opportunity for comparisons of pointers
- Implement optimization pass to remove `__anvill` switch intrinsics HOT 2
- Entry Point Return Addresses on Spec Export HOT 1
- Add a method to TypeProvider that passes in a caller address when looking up a callee function type HOT 1
- Have a way of annotating llvm instructions with the architecture HOT 1
- error linking with doctest lib HOT 2
- DSE and Sinking performance regression in LLVM 14
- Use anvill with IDA Home
- Remove obsolete LLVM version checks
- Rewrite ConvertIntegerToPointerOperations pass to not rely on pointer types
- Possible Regression in Address to Entity Uses
- Build fails with latest Remill HOT 1
- Return Address not eliminated for x86-64 HOT 1
- State escape with fizz_buzz
- Warnings from `test_anvill`
- Document what the compatibility with the new low-level lift architecture is for each pass HOT 5
- a solution tool to the "anvill-specify-bitcode(Currently unsupported)" HOT 1
- python plugin for IDA error: get_context_assignments_for_addr isn't implementation
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