WilbertPol's mooneye-gb tests failing about sameboy

[LIJI32]

That was tested against the libretro core, right? The libretro fork seems to be ~50 commits behind at the moment, so I'd have to test it with the latest code, and again, confirm the CGB results against my CGB-E, as CGB-C and older revisions have an extra PPU bug.

[sczther]

Yep, didn't build myself

[LIJI32]

Tested all of these tests on the latest master, as well as all intr_2_mode0_* tests.

The following tests pass on both DMG and CGB mode:

• intr_2_mode0_timing_sprites
• intr_2_mode0_scx1_timing_nops
• intr_2_mode0_scx2_timing_nops
• intr_2_mode0_scx3_timing_nops
• intr_2_mode0_scx5_timing_nops
• intr_2_mode0_scx6_timing_nops
• intr_2_mode0_scx7_timing_nops

The following tests pass on CGB mode and fail on DMG mode:

• intr_2_mode0_scx4_timing_nops
• intr_2_mode0_scx8_timing_nops

The following tests fail on both:

• intr_2_mode0_timing_sprites_nops
• intr_2_mode0_timing_sprites_scx1_nops
• intr_2_mode0_timing_sprites_scx2_nops
• intr_2_mode0_timing_sprites_scx3_nops
• intr_2_mode0_timing_sprites_scx4_nops

The rest of the tests fail as reported. I still have to confirm those on real hardware, but these should be useful.

[LIJI32]

Funny, seems like intr_2_mode0_scx4_timing_nops and intr_2_mode0_scx8_timing_nops require an original boot ROM to pass. I wonder what's my DMG boot ROM is doing wrong, as these test do work with 4 other boot ROMs tested.

[LIJI32]

Turns out these two failed thanks to a silly (but major) regression. A few more to go.

[sczther]

Okay, I managed to compile the latest master and these are the results:
CGB Failing
intr_0_timing.gb
ly_lyc_0-C.gb
ly_lyc_0_write-C.gb
ly_lyc_153-C.gb
ly_lyc_153_write-C.gb
ly_lyc_write-C.gb
ly_new_frame-C.gb
stat_write_if-C.gb

DMG Failing
intr_0_timing.gb
intr_2_timing.gb
ly00_mode0_2-GS.gb
ly00_mode1_0-GS.gb
ly_lyc_0-GS.gb
ly_lyc_0_write-GS.gb
ly_lyc_write-GS.gb
stat_write_if-GS.gb
timer_if.gb

So, some intertesting regressions. I guess you will have to ponder a bit more about the details of the implemenatation. Best of luck!

[LIJI32]

Fixed intr_0_timing and intr_2_timing, as well as another timing regression in DMG which might affect other tests. intr_0_timingfailed because the very first line ever rendered after turning the display on is glitched, and some edge case of that glitch was not emulated properly. intr_2_timing failed because a PPU bug previously thought to be a CGB-only bug apparently happens on the DMG as well.

[sczther]

UPDATED 1.4.18
I did not retest everything for reggresions, but it probably is down to this now:

CGB Failing
ly_lyc_0-C.gb
ly_lyc_0_write-C.gb
ly_lyc_153-C.gb
ly_lyc_153_write-C.gb
ly_lyc_write-C.gb
ly_new_frame-C.gb

DMG Failing
ly_lyc_0_write-GS.gb
ly_lyc_write-GS.gb

[LIJI32]

It's extremely surprising how many different previously undocumented behaviors were discovered by simply fixing tests in this suit. I just discovered a new quirk that also explains several odd behaviors of the OAM interrupt, and while researching that quirk I wrote a new test ROM that discovered a new edge of the DMG STAT bug.

[sczther]

Yeah, I found out Wilbert Pol is _Judge, so it has been a journey with his testsuits for at least 11 years. He sure knows his stuff! Glad it helps to advance the understanding of GB hardware.
PS: Do you have a place where your test roms are available?

[LIJI32]

I plan releasing them after v0.11

[LIJI32]

Tested currently failing as for the latest commit (testing everything for regressions):

CGB:
ly_new_frame-C
ly_lyc_write-C
ly_lyc_153-C
ly_lyc_0_write-C
ly_lyc_0-C
ly_lyc_153_write-C

DMG:
vblank_stat_intr-GS
ly_lyc_write-GS
ly_lyc_0_write-GS

[LIJI32]

All DMG tests pass now. Some more research is needed for the CGB variant of the LYC write tests. It is also very likely that these tests are revision dependent, as CGB-CPU-D fixed some quirks with how LYC works.