PostRA pseudo scheduling about llvm-mos

[mysterymath]

This should no longer be necessary if we move pseudo expansion into the instruction selector, register allocator, and PEI. The regular machine scheduler and register allocator can handle the first case, while the register scavenger handles the last.

There still may be instruction groupings inserted in inopportune places when the register allocator issues a spill. However, it's ability to re-organize the existing allocation in the face of this should help deal with this when it occurs. In the worst case, maybe we can fudge the store/load instertion locations in store/loadRegTo/FromStackSlot.