Comments (2)
Thanks for commenting. Have to clarify this.
RISC-V is an inspiration in that it defines a simple and stable hardware-software interface. This means that people can implement new hardware with the minimum of fuss for software people who don't need to rewrite their compiler backend for a new instruction sets all the time. So hardware and software implementations can evolve independently over each other.
The NIC world needs to be more like this. Currently it feels more like the old Unix server days where you have lots of vendors - Sun, SGI, IBM, HP, etc - and buying hardware from one of them also means buying into their proprietary instruction set, operating system, C compiler, etc.
So we see the NIC vendors putting a different proprietary hardware-software interface on each model, expecting users to buy into their software ecosystems to use their hardware, and increasingly forming consortia to build Frankenstein-esque mergers of their code. This causes a lot of collateral complications for software people, even though all we want to do is send and receive packets.
We gave a talk on this topic at FOSDEM 2018 (sorry about the audio): https://www.youtube.com/watch?v=sgwt7SmvVWA
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I talked more about this topic at FOSDEM on the weekend. Just a 10-minute talk in the context of ConnectX. https://youtu.be/ZigsHkxMHPo
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Related Issues (14)
- Define Transmit interface HOT 4
- Podcast with Hennessy and Patterson about RISC
- Support multiple read/write cores efficiently
- Benchmark setup for validating design HOT 11
- [Mildy interesting] NIC speed vs. driver lines of code HOT 7
- Hardware for 10G EasyNIC HOT 6
- How a ConnectX device driver works [FOSDEM talk]
- Define the Receive interface
- Conserve PCIe bandwidth HOT 1
- Avoid individual descriptors HOT 3
- Consider adding TX_BLOCK_SIZE register HOT 2
- Eliminate read from transmit path HOT 1
- Avoid streaming non-idempotent register writes? HOT 1
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