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aes_128

AES (Rijndael) IP Core (128 bit version)

cores

Various HDL (Verilog) IP Cores

corundum

Open source, high performance, FPGA-based NIC

darkriscv

opensouce RISC-V implemented from scratch in one night!

dsi_controller

MIPI DSI controller

github520

:kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）

hdmi

Send video/audio over HDMI on an FPGA

mipi_csi2_tx

VHDL code for using Xilinx MGT gigabit transceivers/LVDS lines for MIPI CSI-2 TX protocol

mipi_csi_receiver_fpga

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3

myhdl

The MyHDL development repository

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

prjxray

Documenting the Xilinx 7-series bit-stream format.

riffa

The RIFFA development repository

smartcam

timespec

Functions for working with timespec structures

usb2_dev

USB 2.0 Device IP Core

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-pcie

Verilog PCI express components