m4j0rt0m Goto Github PK

followers: 6.0 following: 11.0 repos: 56.0 gists: 0.0

Type: User

Bio: Senior Research Engineer | CPU Architect | FPGA Enthusiast

Location: Barcelona, Spain

m4j0rt0m's Projects

algol

A RISC-V CPU (Outdated: using priviledge v1.7)

boom-attacks

Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

docker-icestorm

Dockerfile containing Ubuntu 18.04 with the Icestorm toolchain, includes also yosys, arachne-pnr and nextpnr

docker-iverilog

Dockerfile containing Ubuntu 18.04 with Icarus Verilog

docker-quartus_lite

Dockerfile containing Ubuntu 18.04 with Quartus Lite 20.1.1

docker-riscv

Dockerfile containing Ubuntu 18.04 with some RISC-V and Hardware Development tools

docker-spyglass_linter

Dockerfile with Ubuntu 18.04 containing the minimum required libraries to run SpyGlass

docker-verilator

Dockerfile containing Ubuntu 18.04 with Verilator v4.108

This repository provides the necessary files to build and manage a Docker image for Yosys, an open-source Verilog synthesis tool. It includes a Makefile for building, tagging, and pushing the image to Docker Hub.

duckwizard

duckWizard: RTL Development Framework

duckwizard-fpga-altera

RTL Development: Altera FPGA Board Test (Template)

duckwizard-fpga-lattice

RTL Development: Lattice FPGA Board Test (Template)

duckwizard-simulation-iverilog

duckWizard: Simulation with Icarus Verilog

duckwizard-simulation-questasim

duckWizard: Simulation with QuestaSim

duckwizard-simulation-vcs

duckWizard: Simulation with Synopsys VCS

duckwizard-synthesis-quartus

duckWizard: Synthesis with Quartus

duckwizard-synthesis-yosys

duckWizard: Synthesis with Yosys

icebreaker

Small and low cost FPGA educational and development board

icesugar

iCESugar FPGA Board (base on iCE40UP5k)

jk_ff_example

JK-Flip Flop with Clock, Preset and Clear active-low logic (Example)

matrix-index-example

Brief example in how to index a value inside a 2D matrix

missionary_cannibal

Missionary Cannibal Example Project

multi-port_xor-ram

XOR-Based Multi-Port RAM

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