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adas

ADAS高级辅助驾驶的一些项目源码，包括LDW车道偏离预警、前车起步提醒等

ahb2apb-bridge-design

This repository contains the Verliog codes and test bench that I have designed as a part of my internship at Maven Silicon Bengaluru Pvt Ltd. The task was to design an AHB2APB bridge for the AMBA controller. The internship was instructor led.

branch-prediction-programming

🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.

branch-predictor

The project focusses on emulating the behavior of the branch predictors and analyze their performance. The project was done as a part of (ECE 563) Microprocessor architecture course offered by North Carolina State University.

cachesimulator

Cache and Memory Hierarchy Simulator Design

calicam

CaliCam: Calibrated Fisheye Stereo & Mono Camera

cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

computer-architecture-labs

Works of all the labs of Computer Architecture. Contains single-cycle, and pipelined ARM architecture verilog code.

cppvreplkas

A Software-in-the-Loop simulator for a lane keeping assist system (LKAS) using V-REP to validate the LKAS controller and the lane detection algorithm.

hardware-cnn

A convolutional neural network implemented in hardware (verilog)

inverseperspectivemapping_library

C++ class for the computation of plane-to-plane homographies, aka bird's-eye view or IPM, particularly relevant in the field of Advanced Driver Assistance Systems. Using OpenCV 2.x.

kitti_topview_converter

make KITTI velodyne lidar data, label for 3d to top view coordinates

lane-departure-warning-system

A Lane Departure Warning System for Raspberry Pi 3

missing_data_imputer

Builds a dataframe from csv file, inspects for missing data, imputes missing numeric values based on interpolation methodology

ml-accelerators

Topics in Machine Learning Accelerator Design

orb_slam

A Versatile and Accurate Monocular SLAM

physical-design-and-verification-of-dpram-using-sv-uvm-and-semi-custom-design

Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functional coverage and code coverage report

realtime-distance-estimation-using-planar-homography-for-mobile-robot

risc-v-processor

A single cycle processor implemented in Verilog. Final Project for ENG EC413 - Computer Organization (Fall 2019).

risc-v-single-cycle-cpu

A RISC-V 32bit single-cycle CPU written in Logisim

risc_v_single_cycle_processor

My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris and David Harris

riscv

RISC-V CPU Core (RV32IM)

riscv_pipeline_core

This repository contains the design files of RISC-V Pipeline Core

riscv_single_cycle_core

This repository contains the design files of RISC-V Single Cycle Core

robust-topview

Robustly Converting Camera View from Normal View to Top View for Autonomous Vehicle System on Robotics Operating System (ROS)

router-1-x-3-

Router 1 x 3 verilog implementation

router-1x3-rtl-design

Architectural design of data router in verilog

sfm_quality_evaluation

SfM Camera trajectory quality evaluation

stereov3dcode

《立体视觉入门指南》 代码， c++ code for StereoV3D course

structure-from-motion

A simplified version of incremental structure from motion to reconstruct the 3D structure of a scene from a sequence of 2D images