256-bit-modular-adder-subtractor

Hardware Implementation of a Modular Adder/Subtractor

64-bit-single-cycle-risc-v-core

Digital Design and ASIC Implementation of a 64-bit Single Cycle RISC-V Core that supports RV32I ISA

asic-physical-design-roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

asynchronous-fifo

A verilog implementation of an aynchronous FIFO (First In First Out).

awesome-profile-readme-templates

A collection of awesome readme templates to display on your profile

clock-domain-crossing-synchronizers

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing solutions in digital systems.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

design-and-verification-of-a-pcie-packet-detector

Digital Design of a PICe packet detector FSM that detects whether the packet is a good or pad.

fixed-point-multiplications

Several methods are presented in this repository to multiply signed and unsigned operands, including the sequential add-shift method, the Booth algorithm, and an array multiplier.

ghdl

VHDL 2008/93/87 simulator

mahmouodmagdi

memory-system-verilog-class-based-testing-environment

A SystemVerilog Class-Based Testing Environment to test 32*32 Memory Design

modular-inverse

A SystemVerilog Implementation of the Montgomery Modular Inverse with Binary Extended Euclidean Algorithm

modular-multiplier

A System Verilog Design of the Shift-sub Modular Multiplier Algorithm

pdk_onc5

Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

rtl-design-of-arm-based-ahb-to-apb-bridge

Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way

rtl-to-gds-implementaton-of-low-power-configurable-multi-clock-digital-system-

It is resposable of receiving commands through UART receiver to do different system functions as register file reading/writing or doing some processing using ALU block and send result as well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol.

rtl_codes

This Repo. cotains different Verilog Codes of different Logic Units

taskscheduler

a hardware task scheduler design

u-boot-xlnx

The official Xilinx u-boot repository

uart-communication-protocol

Verilog Hierarical Design of the UART

uart-communication-protocol-using-spartan-6-xilinx-fpga