mariuselv Goto Github PK
Name: mariuselv
Type: User
Company: Bitvis / Inventas
Bio: VHDL, Python, UVVM
Location: Norway
mariuselv's Projects
compliance-tests
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
compression
One of the compression methods I created for my Master thesis. Written in Matlab
ghdl
VHDL 2008/93/87 simulator
hdl
HDL libraries and projects
hdltool
HDL Tool is a python program for accelerating VHDL simulations
mariuselv
menu
Testing terminal python menu
nvc
VHDL compiler and simulator
projecteuler
Possible Project Euler solutions
rust_hdl
saveit
Fast and easy note saving from terminal
serial
Python-Arduino serial interface testing
tufte-latex
A Tufte-inspired LaTeX class for producing handouts, papers, and books
uvvm_all
Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
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