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boledu-hls-course-lab_1

Board: PYNQ-Z2, Vitis version: 2021.2

boledu-hls-course-lab_2

Board: PYNQ-Z2/KV260, Vitis version: 2021.2

boledu-hls-course-lab_3

Board: AlveoU50, Vitis version: 2021.2

caie-filter-pruning

Constraint-Aware Importance Estimation for Global Filter Pruning under Multiple Resource Constraints (CVPRW2020)

crash_course_for_new_members

Deep Learning & VLSI Crash Course for New Members

cv_course_tutorial

This is the mini-tutorial of Computer Vision course (Spring 2021)

dl_practice

Deep learning practice for students to play with popular deep learning frameworks.

gratetile

jini-intelligent-computing-lab2

msoc---application-acceleration-with-high-level-synthesis-

This repository is for the co-teaching course "Multimedia System-on-Chip Design" (2020 Fall)

msoc-hls

Multimedia SoC Design with Specialization on Application Acceleration with High-Level-Synthesis [2020 Fall]

nicotb

A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.

ntu_giee_ms_101

M.S. 101, Graduate Institute of Electronics Engineering, National Taiwan University

ntu_giee_phd_101

Ph.D. 101, Graduate Institute of Electronics Engineering, National Taiwan University

ntu_ms_thesis

National Taiwan University Master's Thesis Template (Latex + Word)

ntu_phd_dissertation

National Taiwan University Ph.D. Dissertation Template (Latex + Word)

python_opencv_lab

This is the lab practice for students to get the hang of using python-opencv to do image processing applications.

saf

SAF: Streaming Analytics Framework

seal

Learning Superpixels with Segmentation-Aware Affinity Loss

ste-nvan

Spatially and Temporally Efficient Non-local Attention Network for Video-based Person Re-Identification (BMVC 2019)

svlib

A library with verified, configurable SystemVerilog module set with example

umi

This project implements the paper "Unrolled Memory Inner-Products: An Abstract GPU Operator for Efficient Vision-Related Computations" (ICCV 2017).

vlsi_lab1

RTL + Synthesis + APR

vlsi_lab2

RTL + Verfication + Synthesis + APR