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Name: Rajeev Srivastava
Type: User
Bio: promoting open VLSI
Name: Rajeev Srivastava
Type: User
Bio: promoting open VLSI
clock tree synthesis
A collection of RTL designs in verilog available on the web
smart-irrigation
Sram implementation example
Generate testbench for your verilog module.
This project implements a hardware design of a high speed Multiplier using techniques of Vedic Mathematics that improves the overall performance of any arithmetic unit.
Tools for Verilog HDL development.
A declarative, efficient, and flexible JavaScript library for building user interfaces.
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.