Bug in UART driver about csp

[vishalnxt]

@dchirgwin , thank you for reporting the issue. We are looking into the issue and will get back.

[vishalnxt]

@dchirgwin , This bug got introduced because of a fix done for an errata on PIC32MK devices. On PIC32MK, the transmit interrupt flag does not remain asserted when all characters are transmitted out.

Consider the following scenario, where in the transmit interrupt, after filling the transmit FIFO and before clearing the transmit interrupt flag, another high priority interrupt occurs and the current interrupt execution gets preempted. When the CPU returns back to service the preempted transmit interrupt, all characters may have been transmitted out and the transmit FIFO can be empty. At this point, if the transmit interrupt flag is cleared, then on PIC32MK devices it does not remain asserted even though the condition for the interrupt flag is true. The suggested workaround for this is to clear the interrupt flag before writing to the transmit data register.

However, on devices where the interrupt flag does remain asserted, clearing the interrupt flag while the interrupt condition is true results in interrupt flag getting set again, thereby firing another interrupt. As you rightly mentioned, this gets largely unnoticed because the ISR checks for the txBusyStatus flag and whether the transmit FIFO has space to accept a new character.

Same applies in case of data reception. If the receive interrupt flag is cleared after reading out the receive FIFO and after receiving a new character in the FIFO (again due to another higher priority interrupt preempting the receive interrupt and thereby allowing enough time for a character to be received), then the receive flag remains cleared even though receive FIFO has unread characters.

Hope this provides the clarification.

The issue is fixed now by adding the workaround only for PIC32MK devices. The fix will be part of the next release - v3.8. Thank you again for reporting the issue.

[syamknair]

Fixed as part of v3.8.0