32 bit wide DATA about hyperram

[MJoergen]

Interesting proposal. Thank you for writing.

I suppose one could add a generic to configure the width of the Avalon data bus.

However, I generally prefer to Keep Things Simple (TM). In this particular case, I already have existing designs that need a wider data bus. To solve this I have made use of this module: https://github.com/MJoergen/Avalon/blob/main/avm_decrease.vhd.

So the idea is that you insert this module between your 32-bit client and the 16-bit HyperRAM controller.

This makes for a modular approach, where each module does just one thing. And it is essentially plug-and-play, like playing with Lego bricks :-)

In that repo you may also find a simple read cache: https://github.com/MJoergen/Avalon/blob/main/avm_cache.vhd.

Let me know what you think about this approach.

[AnttiLukats]

Thanks for providing this ERRATA wrapper!

[AnttiLukats]

The proposed method of using avm_decrease.vhd to change the data width to 32 bit works, tested on CR00107 board. But when used with AMD "AXI AMM Bridge" IP core it was necessary to shift the incoming avalon bus address bis down by two bits. After that it worked.