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Name: Mohamed Tarek
Type: User
Bio: ECE student at Ain shams University Cairo, with hands on experience in ASICs & FPGA design flows.
Name: Mohamed Tarek
Type: User
Bio: ECE student at Ain shams University Cairo, with hands on experience in ASICs & FPGA design flows.
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
digital watch based on 555 timer IC and 7447 decoder 74160 BCD counter and 7 segment dispalys
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
RTL to GDSII flow of a low Power configurable multi clock digital system
EIS based solution for sensing Brucella in milk based on ESP32 low cost MCU with MATLAB in the loop affiliated with Ain Shams University IC lab supervised by professor Hani Fikry
Work under progress.
This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented
A repo for my System Verilog testbenches with test benches for UART, I2C, SPI, FIFOs and Bus protocols like AMBA, AHB and WISHBONE
NIOS II controlled hardware ODE solver implemented on Cyclone IV FPGA
The RTL for an SPI slave memory interface
A repository for a quadcopter project
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