msfschaffner Goto Github PK

ariane

Ariane is a 6-stage RISC-V CPU

ariane-sdk

Ariane SDK containing RISC-V tools and Buildroot

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

axi_node

AXI X-Bar

axi_riscv_atomics

AXI Adapter(s) for RISC-V Atomic Operations

cluster_interconnect

common_cells

Common SV components

cpm_pf-1

Coarse to fine Patch Match + Permeability Filter

edalize

An abstraction library for interfacing EDA tools

fpga-support

IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs

fpnew

[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

fpu

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

openpiton

The OpenPiton Platform

opentitan

OpenTitan: Open source silicon root of trust

pycryptodome

A self-contained cryptographic library for Python

riscv-arch-test

riscv-compliance

TEMPORARY FORK of the riscv-compliance repository

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-dbg

RISC-V Debug Support for our PULP Cores

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-fesvr

RISC-V Frontend Server

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-pk

RISC-V Proxy Kernel

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

sat-solver

SAT solver for use in Enstaller, based on the MiniSat implementation

style-guides

lowRISC Style Guides

uvm-components

Contains commonly used UVM components (agents, environments and tests).

verilator

Verilator open-source SystemVerilog simulator and lint system