Introduction

Hi, I’m @mshong, with a Ph.D. degree in electrical engineering.
I worked as an cooperation professor at Korea University for 5 years, teaching Signals and Systems and Discrete Math.
I'm currently employed at Sapien Semiconductor, a fabless company where my work involves algorithm development using Python and IP design using Verilog HDL.
I have been developing video compression technologies, display technology, and image processing mostly.
Lately, I have been interested in machine learning and deep learning with Python.
You can reach me at [email protected].

Recent Verilog HDL Projects:

I have recently developed the following projects using Verilog HDL:

DSC(Display Stream Compression): A video compression standard developed by VESA (Video Electronics Standards Association) that is used to reduce the amount of data needed to transmit high-quality video. More information can be found at DSC.
VDC-M(Video Display Compression M): Another video compression standard developed by VESA that is designed for high-end displays, such as those used in medical and aerospace applications. More information can be found at VDC-M.
De-Mura Compensation: A technique used to compensate for stains that may appear in the process of producing uLED/OLED displays.
Dead Pixel Compensation: A technique used to compensate for dead pixels that may appear in the process of producing uLED/OLED displays.
Bilinear and Bicubic Video Scaler: Algorithms used to increase or decrease the size of an image while maintaining its quality.