Comments (3)
@mumbel should I report issues here with the tricore processor? I am using the December public release but will try and get the build to work for the latest release on W10 as well. No priority as I can get most of what I need by using a combo of IDA and Ghidra. There are still missing code between compiler generated functions:
which should be decoded as:
As well as these type of "off by 1" failure to decode correctly:
Which Ghidra does quite a bit with the last jump statements in a jump table.
You can see from this image that IDA also does analysis of the stack variables as well. I like the Ghidra choice here but others may prefer what IDA does especially in this case where the function cannot be decompiled to C (unknown error)
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Hey, @DarrylC03 , I don't mind looking at bug reports here, but you might eventually get attention from the Ghidra devs if you post an issue there. A lot of stuff, unless an actual instruction decoding bug (for the most part this is all I think I could promise to reasonably help/fix), I just don't know enough fix in most cases.
The last screenshot does seem kind of surprising, I do have a10
listed as the stack pointer, so not sure what to do about that, seems auto analysis would pick that up. The first two are a change in code flow that I'm not sure how Ghidra decides to keep disassembling by address or continue with code flow, I'd think it would attempt to disassemble in those examples too.
One area I'd really like to get some time to spend on is the decompiler, but just haven't yet. things like bad switches and the resulting disconnected code flow and low-level
messages like yours are super frustrating, I get those on other processors too. I really don't know if that's some issue with the SLEIGH I implemented as-is for each instruction or just instructions that regardless of the implementation the decompiler would choke on due to complexity.
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Related Issues (18)
- Add address spaces to processor definition files HOT 2
- Add support for TC277 HOT 5
- Can't build 'tricore' project HOT 2
- Use misa instead for the context
- Use separate git repositories for processor specs HOT 2
- [tricore] float-point in DVADJ operand HOT 2
- [tricore] 64 bit registers in DVINIT instruction HOT 1
- RISC-V fixes
- size of "long" for risc64 HOT 2
- sample files HOT 3
- Test binaries HOT 9
- NOP opcode HOT 1
- tricore/certification.manifest HOT 1
- Possible bad instruction decode HOT 2
- Peripheral register definitions HOT 2
- Base + offset addressing mode HOT 3
- mirror addresses HOT 4
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