dont flush tlb on every map about nanos

[convolvatron]

looks like this was removed (?) should still flush on unmap

[wjhun]

Eric,

Looking in AMD64 Architecture Programmer’s Manual, Volume 2: System Programming, I came across this paragraph (p144):

"Under certain circumstances, an upper-level table entry that cannot ultimately lead to a valid translation (because there are no valid entries in the lower level table to which it points) may also be cached. This can happen while executing down a false path, when an in-progress table walk gets cancelled by the branch mispredict before the low level table entry that would cause a fault is encountered. Said another way, the fact that a page table has no valid entries does not guarantee that upper level table entries won't be accessed and cached in the processor, as long as those upper level entries are marked as present. For this reason, it is not safe to modify an upper level entry, even if no valid lower-level entries exist, without first clearing its present bit, followed by an INVLPG instruction."

Do you take this to mean that we should not be setting the present bit on upper level ptes until the terminal page entry is installed?

[wjhun]

Also relevant from same page:

"InvalidationofCachedUpper-levelEntriesbyINVLPG. TheeffectofINVLPGonTLBcaching of upper-level page table entries is controlled by EFER[TCE] on processors that support the translation cache extension feature. If EFER[TCE] is 0, or if the processor does not support the translation cache extension feature, an INVLPG will flush all upper-level page table entries in the TLB as well as the target PTE. If EFER[TCE] is 1, INVLPG will flush only those upper-level entries that lead to the target PTE, along with the target PTE itself. INVLPGA may flush all upper-level entries regardless of the state of TCE. For further details, see Section 3.1.7 “Extended Feature Enable Register (EFER)” on page 55."

[wjhun]

My hunch is that the entries should be written from the page level up, with the present bit set, such that the table is always in a coherent state. Then, at the end, an INVLPG is issued for the page address.

Since we don't touch any upper-level entries that aren't associated with this page, I don't see why the state of EFER[TCE] would matter.

[wjhun]

Resolved in #62