Comments (3)
Hi @MaryBennett
There are no pre-incremented instructions right now, just the post ones.
from corev-gcc.
For per-* ones, I think I made a mistake and to be really ARM-like, a comma should be added after register name in the parenthesis.
Pre-* cv.lw rd, (rs1, +/- imm/rs2)!
from corev-gcc.
Corresponding pull request has been merged
from corev-gcc.
Related Issues (20)
- illegal operand error for "sw" operation HOT 2
- How to check COREV_CLUSTER for Event Load Instruction HOT 2
- cv-simd-shufflei* incorrect builtin HOT 2
- unrecognized opcode 'csrr' extension 'zicsr' required HOT 6
- illegal operands `flw fa5,t2(s1) is generated from the latest release toolchain (05/Sep) HOT 2
- [XCVmem] Normal register-immediate store not recognized HOT 3
- Incorrect code generation with PULP march with 20231017 release HOT 1
- Hardware Loops march option not recognized HOT 1
- Hardware loops causes relocation truncated to fit: R_RISCV_CVPCREL_UI12 HOT 3
- Hardware loops causes ICE in final_scan_insn_1 HOT 5
- .option norvc is ignored with Zca HOT 2
- xcvmem `mem (reg + reg)` instructions require corev.md to be above movSI. HOT 1
- Add regression tests for hardware loop failures in issues #83 and #84 HOT 1
- cannot find suitable multilib during the build, though it is shown in the toolchain lib folder. HOT 3
- pseudo instruction "LA" not translating to correct instructions HOT 5
- HW Loop produces an ICE during building HOT 2
- Hardware Loops registers not saved/restored before being used in synchronous/asynchronous exception handler HOT 2
- CORE-V bitmanip extract failures with -O1 HOT 1
- CORE-V bitmanip builtin failure with bclr/bset HOT 2
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from corev-gcc.