Question: how to generate the SDC file? about opentimer

[qrqiuren]

It's the timing constraint file that you must define yourself. You can either search for Synopsys' manual or read the book Constraining Designs for Synthesis and Timing Analysis.

[hughperkins]

Hmmm, I wrote my own script in the end https://github.com/hughperkins/VeriGPU/blob/main/verigpu/timing.py Seemed easier than figuring out how to write an sdc file :) Not sure if I'm missing anything from my script that opentimer handles, or handles better? My script estimates both maximum propagation delay, as a ratio of nand gate units; and area, also as a ratio of nand gate units.

[qrqiuren]

I think your understanding is wrong.

The SDC file is the constraint of timing. For example, I want my circuit to run at 100MHz, then I can define a clock in the SDC file of 100MHz and let the compiler (yosys or some other things) optimize the circuit to run at 100MHz. With the resulting netlist and the SDC, the STA tools (like OpenTimer) can check if your circuit meets such requirements.

If you cannot provide an SDC file to the STA tool, it could not perform such analysis because it cannot infer your timing paths.

Just let me show a simple example of defining the clock clk in 100MHz. You can pick it up and try to expand yourself with the manuals and STA books. By the way, the SDC format is just a subset of the Tcl language.

create_clock -period 10 [get_ports {clk} ] -name clk
set_clock_uncertainty -setup 0.1 [get_clocks *]
set_clock_uncertainty -hold 0.1 [get_clocks * ]
set_clock_latency -source -fall -early 0.1 [get_clocks *]
set_clock_latency -source -fall -late 0.1 [get_clocks *]
set_clock_latency 0.5 [get_clocks *]

[qrqiuren]

If you provide such SDC file to yosys, you may export the resulting netlist and the resulting SDC (not the original hand-written SDC). You can let OpenTimer to read them.