Priyanshu Mishra's Projects
[Computer Engineering] Programmable 8-bit computer based on von Neumann architecture, designed and implemented from scratch in Logisim.
RTL code of an 8-bit CPU designed in Verilog with a separate file for each module.
360 view on ai/ml/dl applications
Automatic Mapping Generation, Verification, and Exploration for ISA-based Spatial Accelerators
š§āš« 59 Implementations/tutorials of deep learning papers with side-by-side notes š; including transformers (original, xl, switch, feedback, vit, ...), optimizers (adam, adabelief, ...), gans(cyclegan, stylegan2, ...), š® reinforcement learning (ppo, dqn), capsnet, distillation, ... š§
APB to I2C
Apple Firestorm/Icestorm CPU microarchitecture docs
Apple G13 GPU architecture docs and tools
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Ariane is a 6-stage RISC-V CPU
A curated list of modern Generative Artificial Intelligence projects and services
A one stop repository for generative AI research updates, interview resources, notebooks and much more!
A curated list of Generative AI tools, works, models, and references
A List of Free and Open Source Hardware Verification Tools and Frameworks
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Powering AWS purpose-built machine learning chips. Blazing fast and cost effective, natively integrated into PyTorch and TensorFlow and integrated with your favorite AWS services
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
:link: Some useful websites for programmers.
32-bit Superscalar RISC-V CPU
A Linux-capable RISC-V multicore for and by the world
Branch predictor project for Computer Architecture course. Implementation of state-of-the-art TAGE predictor is included.
BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.
An MLIR-based compiler framework bridges DSLs (domain-specific languages) to DSAs (domain-specific architectures).
Master programming by recreating your favorite technologies from scratch.
BullsEye: A Scalable cache miss calculator for affine programs
Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence
Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory
8-bit Harvard Architecture CPU implemented in ABEL
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.