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ps2tek's Issues

Info about MCH_DRD/MCH_RICM

I'm trying to make a PS2 emulator as a personal project based on your documentation. Firstly I would like to thank you for this amazing resource, it has made PS2 emulation so much more accessible to people like me. However I noticed that after initializing the memory and measuring the clock speed the BIOS reads/writes to 0x1000F430/0x1000F440, for which I haven't found any information. Searching DobieStation I found this snippet of code that writes to MCH_RICM: https://github.com/PSI-Rockin/DobieStation/blob/68dd073e751960fd01c839ac34ce6e056d70024a/src/core/emulator.cpp#L952 which seems similar to how PCSX2 handles it: https://github.com/PCSX2/pcsx2/blob/67299fcd9f0a9a503dcc7826edbe21b19f366361/pcsx2/HwWrite.cpp#L238

So my questions are;

  • What are those registers used for?
  • Why is writing to them so complicated?

Memory Card superblock offsets

Hi. Many thanks for this resource, which has been useful to me.

In the section with the memory card filesystem/superblock info, https://psi-rockin.github.io/ps2tek/#sio2ps2memcardfilesystem, I think the following is incorrect:

384       Memory card type. Should be 2, indicating a PS2 memory card
385       Card flags. Default 52h

I think the offsets should be 336 and 337, not 384 and 385.

Also, have you considered showing the offsets in hex rather than decimal? It makes it easier to look things up in a hex editor! Thanks again.

`MMI` instruction table contains references to other tables, but no footnote to explain them

ps2tek/index.html

Lines 438 to 453 in 04f2a90

<B>MMI</B><BR>
<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0><TR><TD><PRE>
31---------26------------------------------------------5--------0
| = MMI | | function|
------6----------------------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | MADD | MADDU | --- | --- | PLZCW | --- | --- | --- |
001 | *1 | *2 | --- | --- | --- | --- | --- | --- |
010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | --- | --- | --- | --- |
011 | MULT1 | MULTU1| DIV1 | DIVU1 | --- | --- | --- | --- |
100 | MADD1 | MADDU1| --- | --- | --- | --- | --- | --- |
101 | *3 | *4 | --- | --- | --- | --- | --- | --- |
110 | PMFHL | PMTHL | --- | --- | PSLLH | --- | PSRLH | PSRAH |
111 | --- | --- | --- | --- | PSLLW | --- | PSRLW | PSRAW |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
</TD></TR></TABLE><BR>

There's no explanation what *1, *2, *3 and *4 are.
It's somewhat obvious that these will be MMI0, MMI1, MMI2 and MMI3, but it looks like their order is not like that.

By trial and error I seem to have gotten *2 = MMI2; not sure about the rest.

`MMI0` - `MMI3` instruction tables have too many `lo` bits in headers

The lo headers have 3 bits ("000", "001", "010", "011"), but there are only 2 bits (probably; "00", "01", "10", "11"):

ps2tek/index.html

Lines 459 to 467 in 04f2a90

|--000--|--001--|--010--|--011--| lo
000 |PADDW | PSUBW | PCGTW | PMAXW |
001 |PADDH | PSUBH | PCGTH | PMAXH |
010 |PADDB | PSUBB | PCGTB | --- |
011 | --- | --- | --- | --- |
100 |PADDSW |PSUBSW |PEXTLW | PPACW |
101 |PADDSH |PSUBSH |PEXTLH | PPACH |
110 |PADDSB |PSUBSB |PEXTLB | PPACB |
111 | --- | --- | PEXT5 | PPAC5 |

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