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adv_dbg_if

Advanced Debug Interface

afe_readout_subsystem

AFE Readout Subsystem

ai-deck-workshop

apb

APB Logic

apb2apbcomp

Conversion between the PULP apb and the compliant one

apb2per

apb_adv_timer

Advanced timer with APB interface

apb_asynch_cdc

APB asynchronous clock domain crossing

apb_efuse_if

APB based interface to eFUSE macros

apb_event_unit

apb_fll_if

Control interface for FLL

apb_gpio

apb_i2c

apb_interrupt_cntrl

Small and simple APB interrupt controller

apb_node

apb_peripherals

Application-Specific APB Peripherals

apb_pulpino

apb_spi_master

apb_timer

APB Timer Unit

apb_uart

apb_uart_sv

apu_cluster

This project is to be instantiated inside pulp_cluster and wraps all shared processing units.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

archi

archi-host

Host Architecture Abstractions for PULP

archimedes

Architecture for Minimum Energy DNNs at Edge and domain-specific processing(ArchiMEDES)

ariane_timer

Timer compatible with RISC-V Privilege Specification 1.11 (WIP)

astral

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

autotiler

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication