Thie is Verilog-AMS to JSON Automatic Device Model Synthesizer. Additional processing is done via Python scripts to create source code for integration into circuit simulators.

The files in the archive/xmlversion directory are forked from https://github.com/upverter/ADMS which has been used as the basis for other circuit simulation projects.

Files in the admsJSON directory are a derivative work of ADMS under the GNU LGPL Version 2.1. Other files may be subject to other license terms. Please look at the individual files in the project directories to determine their copyright and license terms.

Files in the pyadms Python module are under the Apache License Version 2.0

Reference documentation in the docs directory are copyright the respective owners in the individual files.

Verilog-A files processed through this systems are subject to the License terms of the original authors of those files.

Copyright (C) 2023--2024 DEVSIM LLC

Original code copyright the original authors. The NOTICE file has more license and copyright information.