Better Documentation/Tutorials about veriloggen

[LucasBraganca]

Hi, this would be something like this:

from veriloggen import *

def make_module():
  m = Module('xval')
  i_xval = m.Input('i_xval',12,signed=True)
  e_xval = m.Wire('e_xval',15,signed=True)
  e_xval.assign(Cat(i_xval[11],i_xval,Repeat(Int(0,1,2),2)))
  
  return m

print(make_module().to_verilog())

[xd009642]

I've figured out the issues I currently had. One thing I've failed to figure out how to do is an expression like so:

input wire	signed [(12-1):0] i_xval;
...
wire	signed [(15-1):0]	e_xval;
assign	e_xval = { {i_xval[(12-1)]}, i_xval, {(3-1){1'b0}} };

[xd009642]

That fixed my issue thanks! Is there any appetite for improving the veriloggen docs, and maybe having HTML docs hosted somewhere? Whenever I run into an issue I normally spend time going through tests and examples looking for anything that solves it and then going through the actual code which is less than ideal.

[shtaxxx]

HTML docs hosted somewhere

I should prepare such documents ...

[xd009642]

I've not published any python projects myself that have required docs but pydoc should be able to generate docs from doc comments on classes and methods. It's just a case of doc comments for existing code

[Nic30]

@shtaxxx I am using Sphinx code generator together with readthedocs.io
https://github.com/Nic30/hwtLib/blob/master/docs/conf.py

https://hwtlib.readthedocs.io/en/latest/?badge=latest

I was relatively good and it usually works however you may have to fix some code style of doc in your code. Sphinx can also generate PDF/epub/... and readthedocs.io also supports any files.