Comments (4)
Nic30
commented on May 29, 2024
Can I ask why? (I am just curious.)
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shtaxxx
commented on May 29, 2024
I just thought Circle CI looks more modern than Travis CI, and there is no deep reason.
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Nic30
commented on May 29, 2024
Hello,
I guess you know but travis-ci will not be free in 2 days (not mentioning quite expensive compare to competition). I migrated my projects to CircleCI. I prepared some circleci orbs (script package) to simplify installation and testing.
I finally get coverage reports working as expected.
eg. there https://github.com/Nic30/pyMathBitPrecise
If you find yourself in any trouble I can potentially help.
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shtaxxx
commented on May 29, 2024
Oh, I did not prepare anything at this time. Thanks for your information. I will consider the migration to CircleCI again, and will refer your CI script. Thank you!
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Related Issues (20)
- memcpy between on-chip RAMs HOT 1
- Supporting multiple outstanding DMA requests HOT 1
- Supporting indirect addressing by sink RAM of Thread.Stream HOT 1
- Explicit latency constraint between two stream objects which accesses to external resources outside of the stream. HOT 1
- Infinite read size for stream.source
- Inserting user-defined simulation code for Verilator mode
- Bug of stream.ReduceDiv for signed values
- stream.source with only size without data read
- deleted
- always @ ( * ) combinational block HOT 2
- Support for SystemVerilog Interfaces HOT 2
- Creating input with literal BW in the form of [n:0] instead of [n-1:0]
- to_verilog("file.v") creates two empty lines at beginning of file
- Case statement within combinational block HOT 2
- Creating a combinational sequence
- Slice in Wire with two dimension HOT 1
- Imcompatibility of `Module.Wire` and `Module.TmpWire` regarding the keyword arguments. HOT 1
- Convention violation of AXI Lite protocol on AxiLiteSlave HOT 1
- `types.AxiMaster` should be have a cap of number of outstanding readout transactions. HOT 1
- typo in stream/stypes.py line 52 HOT 1
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