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anycore-riscv-tests

A small suite of tests for AnyCore RISC-V

computer-architecture-learning

dramsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

gem5-bench

A wrapper for simulation with gem5

gem5-risc-v-fs-linux

Repository containing the guide and code for booting RISC-V full system linux using gem5.

gem5-salam

gem5-sst

gem5-tutorial-codespace

gem5-utils

gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

grok-1

Grok open release

ibm-appresentor

IBM Appresentor, an automated design of experiments for scaling workload profiles to the exascale.

ibm-exabounds

IBM ExaBounds, an analytical exascale system model

invisispec-1.0

Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.

linpack-hpl

Linpack: configuration, install, optimization

looppoint

Sampled simulation of multi-threaded applications using LoopPoint methodology

mambo

A low-overhead dynamic binary instrumentation and modification tool for ARM (both AArch32 and AArch64 support) and RISC-V (RV64GC).

mambo-v

MAMBO-V: Dynamic Side-Channel Leakage Analysis on RISC-V

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

parsec-benchmark

PARSEC http://parsec.cs.princeton.edu/ 3.0-beta-20150206 ported to Ubuntu 22.04 and with proper version control and SPLASH2 ported to Buildroot 2017.08 cross compilation (ARM, MIPS, etc.). This repo intends to support all build types and benchmarks.

pinball2elf

pinplay-tools

A collection of C/C++ programs and Python scripts to be used in conjunction with Intel Software Development Emulator (Intel SDE, available externally separately). The purpose is to use record/replay functionality in SDE for program analysis.

qemu-mc

QEMU MicroCheckpointing

qpoints

qpointsriscv

Qemu tracing plugin using SimPoints

rev

RISC-V SST CPU Component

riscv-coremark

Setup scripts and files needed to compile CoreMark on RISC-V

riscv-isa-sim

RISC-V Functional ISA Simulator

riscv-matrix-project

Top project for RISC-V Matrix extension proposal and related opensource implementations.

riscv-spike-raw

Execute raw RISC-V machine code in binary format through Spike.