Comments (1)
Close this one because the readme is sufficient for now
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Related Issues (20)
- Add a Custom Name for CoreIR Generator When Generate Verilog HOT 14
- Cannot get two bit types to wire together regardless of direction? HOT 3
- [RFC] Bit Pattern Support in coreir HOT 6
- Regression in inline commonlib mux verilog generation
- Verilog backend can clobber names when generating instance output port wires
- Having trouble at branch rm-ubuf-master HOT 3
- inline_single_instance pass should maintain instance name HOT 1
- Update JSON for Modern C++
- Why is IEEE compliance for CW floating point add/mul set to 0? HOT 2
- verilog ND-array generation should be packed arrays instead of unpacked arrays. HOT 3
- Add Multiply optimization
- segfault when using prototype components. HOT 44
- [feature request] adding prefix to coreir/commonlib/... verilog modules HOT 4
- add_dummy_inputs pass doesn't work with sliced signals
- Add module longname C API
- Compilation error on Apple M1 chip HOT 11
- Request for CoreIR compatible with Windows. HOT 1
- InstanceVisitorPass does not allow passing in functors that have access to the class object itself.
- Need to change googletest tag from master to main HOT 2
- google test throws sign conversion warnings
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