How to Set Up External Interrupts for Mi-V RV32 in REPL Script? about renode

[mateusz-holenko]

Hi @ChaseWeimer, thanks for asking the question.

The generic RiscV32 model supports standard User/Supervisor/Hypervisor/Machine Software/Timer/External interrupt signals as defined by the RISC-V specification.

In Renode it is possible to support other configuration of interrupt lines at CPU level as well, but this requires preparing a specific model.
For example take a look at Minerva.cs - it extends OnGPIO method and keeps track of all external interrupt lines in the irqPending field and exposes it via custom CSRs.
Please note that this might also require a different interpretation of IRQ lines at tlib-level (e.g., to correctly calculate vector address).

For this CPU the meaning of IRQ lines 0, 1, 2 is different than for a standard RISC-V CPU, but the mechanism for connecting the in repl is exactly the same - see litex_minerva.repl as an example.