LTDC add 2 registers (LTDC_SRCR and LTDC_CDSR ) for stm32h7 support about renode

[mateusz-holenko]

Hi @hattmt, thanks for reporting the issue.

After looking at the STM32H7 reference manual (https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) we are wondering if the proposed implementation is the optimal way of solving the problem.

Wouldn't just implementing the LTDC_CDSR register as returning consecutive values of 0x1, 0x2, 0x4, 0x8, 0x1, 0x2, etc. on each read be enough? The idea would be to imitate a progress in frame display process over time.

Your solution allows simulated software to move forward, but according to the documentation VSYNCS and VBR flags do not seem to be related to each other; is there any particular reason you decided to implement the logic that way or was it just a configuration that worked for you?

[hattmt]

Hi @mateusz-holenko ,

Thank you for your reply.

You are right for the logic i used, it was only for my software simulation , and it is too specific.

So it should be better to immitate the real comportement of this register .

I think that what you proposed to imitate a progress in frame display is the best idea .