Comments (1)
This has been done.
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Related Issues (20)
- [riscv.cpu] Debug Module did not become active. dmcontrol=0x0 HOT 8
- `lt` trigger is not always available
- Tracking RISC-V Debug Spec v0.11 testing HOT 5
- Improve stability of riscv-tests for targets with low remotetimeout value HOT 5
- Failed to write to memory, connecting to spike HOT 7
- load_image returns error 'invalid command' HOT 6
- Q extension support HOT 3
- how to read v register if vslide1down instruction not present HOT 19
- Using the `info reg all` command within gdb returns an `remote failure reply 'E0E'` HOT 10
- Issues Flashing Baremetal Applications Directly with OpenOCD on MPFS HOT 2
- Cache information about abstract access availability on per-register basis
- Implement controls to adjust OpenOCD behavior during when it tries to detect which watch point was hit (riscv_hit_watchpoint)
- How can I build openocd with static libs? HOT 13
- Investigate the semantics of step/resume operations in context of HW trigger state.
- `read_memory_bus_v1()` is broken HOT 1
- RISC-V v0.11: Writes to register `x0` (`zero`) should not be cached.
- progbuf issue HOT 7
- Unnecessary calls to `select_dmi()`
- Some header guards do not comply to style guide
- All `targets/RISC-V/spike32.py` tests failing HOT 6
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