Comments (4)
I think OpenOCD should just figure out how to halt the harts as it can't do anything without them halted.
from riscv-openocd.
Raw OpenOCD supports reading registers, memory, etc without halting harts. Not sure how this is reflected in GDB.
from riscv-openocd.
AFAICT gdb's behavior sucks if it connects to a running target. It appears to assume the target is halted, and doesn't attempt to verify this in any way. The best solution seems to be to halt the target in the OpenOCD config script. I'm not sure if there's anything really to do, unless somebody can point us at an example of how it can work better.
from riscv-openocd.
Ok, then maybe we should just close this issue.
from riscv-openocd.
Related Issues (20)
- Failed to write to memory, connecting to spike HOT 7
- load_image returns error 'invalid command' HOT 6
- Q extension support HOT 3
- how to read v register if vslide1down instruction not present HOT 19
- Using the `info reg all` command within gdb returns an `remote failure reply 'E0E'` HOT 10
- Issues Flashing Baremetal Applications Directly with OpenOCD on MPFS HOT 2
- Cache information about abstract access availability on per-register basis
- Implement controls to adjust OpenOCD behavior during when it tries to detect which watch point was hit (riscv_hit_watchpoint)
- How can I build openocd with static libs? HOT 13
- Investigate the semantics of step/resume operations in context of HW trigger state.
- `read_memory_bus_v1()` is broken HOT 1
- RISC-V v0.11: Writes to register `x0` (`zero`) should not be cached.
- progbuf issue HOT 7
- Unnecessary calls to `select_dmi()`
- Some header guards do not comply to style guide
- All `targets/RISC-V/spike32.py` tests failing HOT 6
- openocd only supports Debug Module version 2 (0.13) and 3 (1.0), not 0 (dmstatus=0x0). This error might be caused by a JTAG signal issue. Try reducing the JTAG clock speed HOT 12
- read_memory_bus_v1 does not work properly for sizes greater than 4 HOT 1
- There are cases when WPs disabled by `disable_triggers()` can not be re-enabled by `enable_triggers()`. HOT 2
- How to program multiple cores using Openocd ? HOT 3
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