Comments (1)
aamartin0000
commented on August 15, 2024
When LMUL=4, "v0" of the instruction incudes {v3,v2,v1,v0}, so potentially v2 could be clobbered during the operation-- this is an illegal overlap, because the end result in {v3,v2,v1,v0} would be dependent on the order of operations. If you used v4 instead of v2, this would be legal.
from riscv-isa-sim.
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