Comments (4)
Yep. Probably something that can be fed both to Spike and to our hardware implementations (to be baked into ROM at synthesis time, in that case). But we're gonna hold off until after debug is fully implemented and the current HTIF is kaput.
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That said, ELF is a pretty reasonable file format for this task.
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My organization has a direct application for this feature -- we have a codebase that needs to be kept to minimal size, and the code to build and parse ELF headers is both unnecessary and a potential security hazard to us.
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I just pushed changes that make gdb work with 32-bit spike at
https://github.com/riscv/riscv-isa-sim/tree/debug so now both 32- and
64-bit are supported.
You can use this with gdb's restore command to load code straight from eg.
ihex or srec files. If you try it, let me know how it goes.
Tim
On Sat, Jun 11, 2016 at 10:55 AM, Mark Friedenbach <[email protected]
wrote:
My organization has a direct application for this feature -- we have a
codebase that needs to be kept to minimal size, and the code to build and
parse ELF headers is both unnecessary and a potential security hazard to us.—
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#45 (comment),
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Related Issues (20)
- spike cache model
- Dependency file in makefile is missing
- Incorrect IRQ priority with LCOF
- Deprecated dcsr.halt HOT 2
- Dose write-only operation to csr_seed trigger illegal instruction exception ? HOT 1
- htif : elf load , invalid address
- Possible to forward a Ctrl-C to the running program?
- spike.cfg : remote_bitbang host localhost should be remote_bitbang_host in OPENOCD's
- SPIKE functions use in System verilog HOT 2
- uint64_t
- Why menvcfg.pbmt is set 1 on reset ? HOT 5
- Need assistance for Executing my targeted workload on spike RISC-V ISA after adding custom trigonometric Instructions HOT 5
- From double trap spec, we saw that Ssdbltrp adds an SDT field to sstatus. But will mstatus has this bit? HOT 2
- Segmentation Fault when interrupt handled while interrupts are disabled in machine mode HOT 3
- Commit 584f8551 appears to break enabling the virtualization extension. HOT 1
- Zicntr not listed as supported extension HOT 2
- Spike does not implement the functions of VTA and MTA for "Written with 1s" HOT 8
- `fsqrt.s` with zero source register results `NaN` instead of `0` HOT 3
- Illegal Instruction overlap difference between vfwadd_wf and vwadd_wx HOT 1
- How to change vector extension configuration(vlen, elen)? HOT 4
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