Jayaraman rp

@rpjayaraman · User

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HW Engineer

Samsung SemiconductorIndia35 followers20 repositories

Repositories

rpjayaraman/WTB

Design Verification Interview Combat Arena

★ 1JavaScriptForks 0

rpjayaraman/DV-resource

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

★ 73Forks 11

rpjayaraman/RTL2UVM

Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

★ 35SystemVerilogForks 7

rpjayaraman/LLMxVLSI

Generate, Simulate & Summarize Verilog Code with GenAI and Iverilog tool

★ 6PythonForks 1

rpjayaraman/ZeroToUVM-Verilator

For many engineers and students, the primary barrier to entry for open-source verifi cation is not the methodology itself, but the toolchain. This repo introduces a "one-shot" automation framework designed to take users from zero to a working, Verilator-compatible UVM testbench— with visualization.

★ 3ShellForks 0

rpjayaraman/uvm2pyuvm

uvm2pyuvm is a Python-based tool to automate the conversion of UVM SystemVerilog code into PyUVM Python code

★ 1PythonForks 0

rpjayaraman/VERILATOR_UVM

This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpjayaraman/RTL2UVM) framework.

★ 21ShellForks 3

rpjayaraman/lint-based-uvm_tb_generator

This python script uses pyslang module to parse design file and collects input,output and parameter information. Based on the data, the tb_creator script will generate UVM based testbench.

★ 3SystemVerilogForks 1