Why are exceptions with shared resources not allowed when compiling for thumbv6? about rtic

[n8tlarsen]

Or am I confusing the definition of "exceptions" and "panics"? Is this instead related to #105?

[korken89]

Indeed, you are confusing exceptions and panics.

Exceptions are the exception interrupts in the Cortex-M core, and has nothing to do with panics. :)
The issue with exceptions and v6 is that source masking does not work atomically there, so the locking has a race-condition if we were to allow it.
Hence the error you are getting. :)

[n8tlarsen]

Thanks for getting back to me :)

1. I know the lock used to set PRIMASK when using Armv6-M which is atomic; does it now mask individual interrupts using NVIC_ISER and NVIC_ICER?
2. If the lock were to mask individual interrupts, I'm not following how the non-atomic read, modify, write of NVIC_ISER and NVIC_ICER would cause a data race, since preempting exceptions which modify the NVIC interrupt enable state should return the state when leaving its context.

[n8tlarsen]

Binding tasks to core exceptions, SysTick, HardFault, SVPend, SVCall, etc result in this error. Core exceptions are not maskable by the NVIC (which handles locking in Armv6m) so sharing data between an exception handler and another task causes the data race. Maybe this error message could be improved to specify something like "core exceptions" to point toward those exceptions which are handled directly by the CPU core, rather than the NVIC.

[perlindgren]

Once the under the hood docs are done, we could consider pointing the reader to the docs for an in depth explanation.

[perlindgren]

We close this for now awaiting documentation.