Error @ make BOARD=kc705 about bluespecpcie

[sangwoojun]

Ah this was an issue caused by the open source version of Bluespec removing the previously supplied libraries.

I have removed the dependencies at least for the projects "simple", "dramtest", "dmatest", and "streaming"
I hope this helps!

[kkarthik976]

Thanks for your quick response !
Still i found some issues and will mention in detail as below, Please do the needful...

simple :
[test@test simple]$ make BOARD=kc705
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D
kc705 -remove-dollar -p +:../..//src/ -p +:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
Error: "../..//src//PcieCtrl.bsv", line 23, column 8: (S0000)
Cannot find package `Scoreboard'
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

dramtest :
[test@test dramtest]$ make BOARD=kc705
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D kc705 -remove-dollar -p +:../..//src/ -p +:../..//dram/src/:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
Error: "../..//src//PcieCtrl.bsv", line 23, column 8: (S0000)
Cannot find package `Scoreboard'
../..//buildtools//Makefile.base:18: recipe for target 'all' failed

dmatest :
[test@test dmatest]$ make BOARD=kc705
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D kc705 -remove-dollar -p +:../..//src/ -p +:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
Error: "../..//src//PcieCtrl.bsv", line 23, column 8: (S0000)
Cannot find package `Scoreboard'
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

streaming :
[test@test streaming]$ make BOARD=kc705
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D kc705 -remove-dollar -p +:../..//src/ -D INSTREAMS=2 -D OUTSTREAMS=2 -p +:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
Error: "../..//src//PcieCtrl.bsv", line 23, column 8: (S0000)
Cannot find package Scoreboard'** Error: "./HwMain.bsv", line 9, column 8: (S0000) **Cannot find package Serializer'
Error: "./HwMain.bsv", line 12, column 8: (S0000)
Cannot find package `LZAHCompression'
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

[sangwoojun]

Ah it seems I had not updated the README regarding the new requirements...
bluespecpcie requires the bluelib repository, which must be cloned at the same level as bluespecpcie as default
So if you have bluespecpcie cloned at ~/, bluelib needs to be cloned at ~/ as well
Bluelib can be found here: https://github.com/sangwoojun/bluelib

[kkarthik976]

Hi,
I have cloned bluelib also and got the following errors

[test@test simple]$ make
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D
kc705 -remove-dollar -p +:../..//src/ -p +:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
All packages are up to date.
cp ../..//buildtools//vivado-impl-kc705.tcl ./kc705/impl.tcl
cp user-ip.tcl kc705/ || :
cd kc705; cd verilog/top; ../../../../..//buildtools//verilogcopy.sh; cd ../../; vivado -mode batch -source impl.tcl -tclargs
../../../../..//buildtools//verilogcopy.sh: line 24: cd: /Verilog: No such file or directory
SyncResetA.v
cp: cannot stat 'SyncResetA.v': No such file or directory
SyncRegister.v
cp: cannot stat 'SyncRegister.v': No such file or directory
SyncHandshake.v
cp: cannot stat 'SyncHandshake.v': No such file or directory
MakeReset0.v
cp: cannot stat 'MakeReset0.v': No such file or directory
MakeResetA.v
cp: cannot stat 'MakeResetA.v': No such file or directory
SizedFIFO.v
cp: cannot stat 'SizedFIFO.v': No such file or directory
Counter.v
cp: cannot stat 'Counter.v': No such file or directory
TriState.v
cp: cannot stat 'TriState.v': No such file or directory
FIFO2.v
cp: cannot stat 'FIFO2.v': No such file or directory
ResetInverter.v
cp: cannot stat 'ResetInverter.v': No such file or directory
SyncFIFO.v
cp: cannot stat 'SyncFIFO.v': No such file or directory
ClockDiv.v
cp: cannot stat 'ClockDiv.v': No such file or directory
ResetEither.v
cp: cannot stat 'ResetEither.v': No such file or directory
MakeReset.v
cp: cannot stat 'MakeReset.v': No such file or directory
SyncReset0.v
cp: cannot stat 'SyncReset0.v': No such file or directory
BRAM2.v
cp: cannot stat 'BRAM2.v': No such file or directory
SyncWire.v
cp: cannot stat 'SyncWire.v': No such file or directory

****** Vivado v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source impl.tcl

set_param general.maxThreads 8

set boardname kc705

set pciedir ../../../

if { $::argc > 0 } {

set pciedir [lindex $argv 0]

puts $pciedir

} else {

puts "using default pcie core path"

}

using default pcie core path

set outputDir ./hw

file mkdir $outputDir

set partname {xc7k325tffg900-2}

read_verilog [ glob {verilog/top/*.v} ]

set_property part $partname [current_project]

read_ip $pciedir/core/kc705/pcie_7x_0/pcie_7x_0.xci

INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx_2018.2/Vivado/2018.2/data/ip'.

read_verilog [ glob $pciedir/src/*.v ]

read_xdc $pciedir/src/xilinx_pcie_7x_ep_x8g2_KC705.xdc

if { [file exists "user-ip.tcl"] == 1} {

source user-ip.tcl

}

synth_design -name mkProjectTop -top mkProjectTop -part $partname -flatten rebuilt

Command: synth_design -name mkProjectTop -top mkProjectTop -part xc7k325tffg900-2 -flatten rebuilt
Starting synth_design
ERROR: [Synth 8-439] module 'FIFO2' not found [/home/test/bluespecpcie/examples/simple/kc705/verilog/top/mkProjectTop.v:1750]
Parameter width bound to: 1 - type: integer
Parameter guarded bound to: 1'b1
ERROR: [Synth 8-6156] failed synthesizing module 'mkProjectTop' [/home/test/bluespecpcie/examples/simple/kc705/verilog/top/mkProjectTop.v:3
8]

Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1383.066 ; gain = 126.625 ; free physical = 226
37 ; free virtual = 240165

RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
31 Infos, 8 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Thu Feb 4 17:12:11 2021...
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

[sangwoojun]

Another interesting find! All of the current users have been using the same setup script so these kind of bugs went by undiscovered...
Thanks for that, and sorry things are not smooth for you.

To fix that issue, you need to set an environment variable "BLUESPECDIR", which I think bluespec actually depends on to function correctly.
Depending on where your bluespec installation is, try setting BLUESPECDIR to the lib directory under that
For example, my installation is at:
export BLUESPECDIR=/opt/Bluespec/bsc/inst/lib/

[kkarthik976]

Thanks for your quick response!
I have successfully generated a bitstream for simple and dmatest and will test the same on the hardware. Got errors for dramtest & float projects.

dramtest :
ERROR: [Vivado 12-172] File or Directory '/home/test/bluespecpcie/dram/kc705/core/ddr3_0/ddr3_0.xci' does not exist

while executing

"source user-ip.tcl"
invoked from within
"if { [file exists "user-ip.tcl"] == 1} {
source user-ip.tcl
}"
(file "impl.tcl" line 30)
INFO: [Common 17-206] Exiting Vivado at Fri Feb 5 11:05:25 2021...
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

float :
[test@test float]$ make -j16
mkdir -p kc705
mkdir -p kc705/obj
mkdir -p kc705/verilog/top
bsc -show-schedule -aggressive-conditions -bdir ./kc705/obj -vdir ./kc705/verilog/top -simdir ./kc705/obj -info-dir ./kc705 -fdir ./kc705 -D kc705 -remove-dollar -p +:../..//src/ -p +:../..//../bluelib/src// -verilog -u -g mkProjectTop Top.bsv
checking package dependencies
Error: "Top.bsv", line 6, column 8: (S0000)
Cannot find package Xilinx' Error: "Top.bsv", line 7, column 8: (S0000) Cannot find package XilinxCells'
Error: "./HwMain.bsv", line 11, column 8: (S0000)
Cannot find package `DMASplitter'
../..//buildtools//Makefile.base:18: recipe for target 'all' failed
make: *** [all] Error 1

[sangwoojun]

To use DRAM you need to generate the DDR3 core.
Go to bluespecpcie/dram/kc705 and run make
That should fix that

For floats, you need to generate the floating point cores
Go to bluelib/src/coregen and run ./gen-kc705.sh
That should fix that

There are so much documentation (or makefiles) I should fix!

[kkarthik976]

Thanks for your help.