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beagle_sdr_gps

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

cla_check

digital-hardware-modelling

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

dsp-rtl-lib

RTL Verilog library for various DSP modules

fpga-fft

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

gnsssdr

Automatically exported from code.google.com/p/gnsssdr

gps-sdr-sim

Software-Defined GPS Signal Simulator

inductor-generator

inkscapecircuitsymbols

Inkscape extension to assist creating circuit symbols.

meep

free finite-difference time-domain (FDTD) software for electromagnetic simulations

openserdes

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

pinout

An open source Python package that generates hardware pinout diagrams as SVG images.

pymoschar

Python port of Prof. Boris Murmann's gm/ID Starter Kit

qucs-rflayout

Export Qucs RF schematics to KiCad layouts & OpenEMS scripts

r22sdf

Pipeline FFT Implementation in Verilog HDL

rtklib

silice

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

tbgen

Generate testbench for your verilog module.

teroshdl

The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.