A basic setup for generating HLS projects.
This repo acts as a template for creating new HLS project.
To generate the project, follow these steps:
- Open Vitis HLS Command Line
- Change directory to
hls-project
location - Start a Vitis HLS tcl Command Line with
vitis_hls -f
- (Optional) Obtain your FPGA's part number. Call
list_part
to obtain supported FPGA families. Find your FPGA family and then calllist_part <family>
in order to obtain supported FPGA parts. - In
checkout.tcl
changeVitis HLS Project User Settings
variables to reflect custom project (FPGA part and clk period (in ns)) - In
checkout.tcl
changeVitis HLS IP Package Settings
variables to customize the package process (IP version, name, description and vendor) - Run
source checkout.tcl
If you don't need to access the tcl command line, the checkout script can be sourced with vitis_hls -f checkout.tcl
alone.