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airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-release

Chisel release tooling

chisel-tutorial

chisel tutorial exercises and answers

common_cells

Common SystemVerilog components

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

draw_uml

Drawing the Unified Modeling Language of Rack

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

huancun

Open-source high-performance non-blocking cache

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

linux-on-litex-vexriscv

Linux on LiteX-VexRiscv

memguard

Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-core Processors

naxriscv

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

opensbi

RISC-V Open Source Supervisor Binary Interface

orconf

OpenRISC Conference Website

pipelined_cpu_risc-v

Pipelined CPU for RISC-V architecture(RV32I)

pythondata-cpu-naxriscv

Python module containing verilog files/generators for NaxRiscv CPU (for use with LiteX).

qtcore-c1

riftcore

RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System

risc-666

RISC-V user-mode emulator that runs DooM

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-vp

RISC-V Virtual Prototype

riscv64-debian-linux-on-fpga-with-litex

How to run RISCV64 Debian linux on an FPGA with Litex

rocket-chip

Rocket Chip Generator

rocket-chip-inclusive-cache

An RTL generator for a last-level shared inclusive TileLink cache controller

rpu

Basic RISC-V CPU implementation in VHDL.