About the Csr registers in Vexriscv about vexriscv

[Dolu1990]

Hi, your issue is purly software for now. This isn't realted to VexRiscv
Personnaly i'm using that to read CSR :
https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.3/software/standalone/driver/riscv.h#L89

[ic-hjx]

I am sorry for that I have open the issue in a wrong place. My questions about the Csr registers in VexRISCV mainly pertain to the identification numbers corresponding to different registers, in the program description that I can found in riscv.h :

#define RDCYCLE 0xC00 //Read-only cycle Cycle counter for RDCYCLE instruction.
#define RDTIME 0xC01 //Read-only time Timer for RDTIME instruction.
#define RDINSTRET 0xC02 //Read-only instret Instructions-retired counter for RDINSTRET instruction.
#define RDCYCLEH 0xC80 //Read-only cycleh Upper 32 bits of cycle, RV32I only.
#define RDTIMEH 0xC81 //Read-only timeh Upper 32 bits of time, RV32I only.
#define RDINSTRETH 0xC82 //Read-only instreth Upper 32 bits of instret, RV32I only.

Now I understand that VexRISCV supports the standard Csr register configuration, which has resolved my issue. Thank you very much!