stanly1012 Goto Github PK
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stanly1012's Projects
2019-spring-gt
Project template of course - Graph Theory (EE6622E) in National Cheng Kung University.
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
biriscv
32-bit Superscalar RISC-V CPU
hardware-implementation-of-aes-verilog
Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
lenet_accelerator
A Lenet ASIC Accelerator targeting minimum number of cycles
ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
riftcore
RiftCore is a 9-stage, multi-issue, out of order 64-bits RISC-V Core, which supports RV64IMC.
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
rv32-core
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
superscalar-riscv-cpu
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
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