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alpha-release

Builds, flow and designs for the alpha release

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.9, working as a coprocessor to CORE-V's CVA6 core

black-parrot

Black Parrot is coming soon.

bp-tests

bsg_tapeout_v1_tsmc40

gdspy

Python module for creating GDSII stream files, usually CAD layouts.

gitignore

A collection of useful .gitignore templates

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

lastlayer

Towards Hardware and Software Continuous Integration

myhdl

The MyHDL development repository

netlistsvg

draws an SVG schematic from a JSON netlist

onnx

Open standard for machine learning interoperability

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

openroad-flow

OpenROAD's top level repo pointing to stable binaries, code, sample designs and an example flow

pyparsing

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

qmk_firmware

Open-source keyboard firmware for Atmel AVR and Arm USB families

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

tcllib

tcllib (Mirror of core.tcl-lang.org).

tcloo

Tcl OO Package (for Tcl 8.5, integrated in 8.6). (Mirror of core.tcl-lang.org)

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

yosys

Yosys Open SYnthesis Suite