Delay on RSYNC + 220 max colorclock? about stella

[thrust26]

I can only answer the last question: INTIM is a register which can only be read. The other ones are for @DirtyHairy.

[DirtyHairy]

Howdy! Where do you get the notion that the color clock only counts to 220? It definitely counts to 228 😏 However, Stella steps instruction by instruction, so if you step an instruction with three cycles (= nine color clocks) starting at 220, it'll wrap in this step.

As for rsync, the color clock counter is set to 225 in the cycle in which the write is executed, so it will wrap to zero the next cycle. The behaviour was originally determined with test programs, the only way to find a deeper explanation is to go into the schematics.

[Thomas-de-Bock]

Oooh I'm blind it said unwind 4 cycles but I forgot to convert it to the color clock my apologies. Also I see, I thought when it said "This address resets the horizontal sync counter to define the beginning of horizontal blank time" It was referring to the previous HBLANK, your explanation makes sense. And I understand INTIM is read only, I just thought since its assigned a random value at start there would be some way of changing that starting value, but I guess that could maybe be done with savestates? Anyways thanks so much for responding that clears some things up!

[Thomas-de-Bock]

Wait, sorry to bother again, but if RSYNC sets the colorclock to 225 on the same cycle as the write occured, how can this happen? (Pitfall):

Only after TXS does it wrap around, after the write to RSYNC nothing out of the ordinary happens to the color clock.

[thrust26]

#5 😄