Comments (4)
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The "syntax" is a horrible hack that was superceded by the
much cleaner (* ... *) syntax for attributes, but it is still
used a lot, so I do try to support it. So no, there is not
really any consistent documentation for the syntax.
It looks like what you are doing should work, though, so I'll
take a look and try to see what's up.
On 08/08/2014 06:23 AM, Clifford Wolf wrote:
The following module
|module test(output reg [7:0] y); initial begin // synthesis
translate_off y <= 42; // synthesis translate_on end endmodule |results in the following syntax error (iverilog git 0f294cb
0f294cb):|test.v:3: syntax error test.v:3: Syntax in assignment statement
l-value. test.v:4: syntax error |I'm not sure if there is any kind of formal definition for the
|synthesis translate_off| / |synthesis translate_on| comments, but
the lattice lm32 CPU
https://github.com/m-labs/lm32/blob/master/rtl/lm32_load_store_unit.vis using them inside behavioral code like in my example.
— Reply to this email directly or view it on GitHub
#36.
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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from iverilog.
In Yosys they are handled in the lexer as a special form of comment block. Recently I found this in some user code:
//synopsys translate_off
`include "timescale_x.v"
//synopsys translate_on
Because in yosys the `include is interpreted by the pre processor (which is run before the lexer of course), it is executed in yosys. I'm not sure what "the right thing to do" is in this cases like this (and many others that I could come up with, but this one I actually found). Any suggestions?
Funny detail: There is no "timescale_x.v". So the yosys pre-processor created an `error for that. But this was ignored because the lexer was skipping the "translate_off" block. I only noticed this piece of code because a bug in the pre-processor caused an off-by-one error in a line number for an error later in that file.
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In Icarus Verilog they are handled in the lexor, but they mark
a flag instead of actually turning translation off. What is between
the off/on is still parsed and elaborated, but it is all marked
with an (* ivl_synthesis_off *) attribute to prevent synthesis.
On 08/08/2014 06:22 PM, Clifford Wolf wrote:
In Yosys they are handled in the lexer as a special form of
comment block. Recently I found this in some user code:|//synopsys translate_off `include "timescale_x.v" //synopsys
translate_on |Because in yosys the `include is interpreted by the pre processor
(which is run before the lexer of course), it is executed in yosys.
I'm not sure what "the right thing to do" is in this cases like
this (and many others that I could come up with, but this one I
actually found). Any suggestions?Funny detail: There is no "timescale_x.v". So the yosys
pre-processor created an `error for that. But this was ignored
because the lexer was skipping the "translate_off" block. I only
noticed this piece of code because a bug in the pre-processor
caused an off-by-one error in a line number for an error later in
that file.— Reply to this email directly or view it on GitHub
#36 (comment).
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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=y7EH
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from iverilog.
Should be fixed in git master, now. I've fixed it to be handled in the lexor, instead of in the parser, which in retrospect was a bad idea.
from iverilog.
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