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activity---simulation-based-verification-

This repository consists of Verilog RTL modules and test-bench, used for simulating the FSM mentioned on ICARUS Verilog and compute Code Coverage on the COVERED tool, based upon the State Machine activity problem statement mentioned in Chapter-Simulation Based Verification in the book "RTL-to-GDS" authored by Dr. Sneh Saurabh sir.

ahb-tl-bridge-amicro

SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge

ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

ahbl2avlmm

AHB-Lite to Avalon Memory-Mapped Bridge

altera

altera DE 0 Nano work

amba_axi_ahb_apb_uvm

AMBA bus lecture material

apb-spi-controller-verification

UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC24xx microcontroller specification.

apb_protocol_training_uvm

arbiter-verification

A comprehensive testbench for a round-robin arbiter.

asfigo_sva_verilator

Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.

assert_noc_rtl_sva

Assertion based Network on Chip Security Implementation

autocc_fv_univ

Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operates at RTL to exhaustively examine any machine state left by a process after a context switch that creates an execution difference.

autosva_fv_univ

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

avmm_sha3

UVM testbench for an sha3 implementation with Avalon MM interface

axi_uvm_kumarrishav14

VIP for AXI Protocol

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

blockwork

An opinionated build environment for EDA projects

caravel_ft8_receiver

A fully-integrated FT8 protocol receiver on 130nm CMOS

cdc_components

Collection of different designs for clock domain crossing

cdc_mcp

Multi-Cycle Path (MCP) formulation for CDC(Clock Domain Crossing) Problem

chiptester

Team I's chip tester

code_to_ivl_team

cordic_sdf

Digital System Design Project - Spring 2020

digital-calibration-of-sar-adc

Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)

ecen_689

eda-log-file-warning-suppressor

Suppresses warnings in EDA logfiles.

fcs

Verilog implementation of Ethernet Frame Check Sequence (FCS) with SystemC unit tests

fir_filter-fault-tolerant

N-modular redundancy FIR Filter with fault modeling and injection

fpgasimulation

Example files for the book FPGA SIMULATION

fpuvm

UVM for FPGA - code base