Comments (1)
Apologies, the error was elsewhere, was truncating the readdata elsewhere to 16 bit. The above works in verilator. Will test on hardware.
Rob.
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Related Issues (20)
- Possible preprocessor problem. HOT 3
- Recursive algorithm support? HOT 2
- commit 477301ae regressed my code with obscure error message HOT 6
- Expression trackers in algorithms body lead to confusing (albeit correct) semantics
- Combinational loops may be wrongly detected when passing entire groups as parameters
- Double check initializers for tables HOT 1
- Silice installs files back into the build directory HOT 3
- pipeline sync
- interleaving pipelined algorithms in host pipelines HOT 1
- Extracting bits from a bitfield results in a segmentation fault HOT 2
- Combining declaration and always assignment
- Many boards share a common set of features, yet each board has its own define HOT 2
- Empty FSM states could be optimized HOT 7
- Unused states that remain and cycles that could be avoided HOT 35
- Unexpected code execution. HOT 4
- Name shadowing
- Error initialising bram not brom
- A subroutine which is never called in a design can crash Silice. HOT 6
- Not setting a subroutines output parameter leads to a yosys error. HOT 2
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