no vcd trace about riscv-formal

[towoe]

I created a pull request in YosysHQ/sby#18.
It works for me, but might not be the correct solution.

[cliffordwolf]

I don't know what "exercise 1" refers to. But I'm certain YosysHQ/sby#18. just breaks the tool and doesn't help in any way.

[cliffordwolf]

Ah, apparently "exercise 1" refers to the quickstart guide.

Since you did not post anything that would allow me to reproduce whatever you are seeing, I can only assume that the check passed (because either you didn't change the core, or changed it in a way that had no negative effect), and a passing test of course doesn't produce a counter example trace.

[towoe]

Thanks for the quick reply. Yes, I was referring to the quickstart guide, sorry for not mentioning this.
I did change the core and one test failed.
I changed the core now at a different point and now the trace is generated. This difference is that in the previous failed test, it already stopped at "Warmup failed!". I guess this is a point where there are no traces which can be generated.

[cliffordwolf]

it already stopped at "Warmup failed!". I guess this is a point where there are no traces which can be generated.

yes. I don't know which check exactly failed for you and why of course, but the general idea behind "Warmup failed" is like this: Say you have a check that makes sure that the addi instruction does the right thing. Now you make a change that entirely prevents the core from every handling an addi instruction. This will make the check fail, but there is no counter-example trace showing that the addi instruction is handled incorrectly because there is not even any trace that has the core retiring an addi instructions, correctly or incorrectly.

In more formal terms: If the "warmup check" is enabled (which is the case by default in smt-based symbiyosys flows), then "warmup failed" indicates that no trace satisfying the assumptions exists. (Without the "warump check" those tests pass because the assertions are trivially true if there is a contradiction in your assumptions.)

[towoe]

Now you make a change that entirely prevents the core from every handling an addi instruction.

That is exactly what I did at first. Thanks a lot for the thorough explanation!