Endianness Confusion Load Inst test about riscv-formal

[cliffordwolf]

This looks like you don't have RISCV_FORMAL_ALIGNED_MEM set, but are testing a core that would need this setting to be enabled. See https://github.com/cliffordwolf/riscv-formal/blob/master/docs/config.md#riscv_formal_aligned_mem for details.

Edit: Other way around. It looks like you have RISCV_FORMAL_ALIGNED_MEM set but are testing a core that doesn't need it. :)

[mdxg]

Thanks fixed it :)