Comments (3)
Just looking at the first one: The spec says that C.LI with rd=0 is a hint instruction, not a reserved opcode.
If your core decodes C.LI with rd=0 as illegal instruction then your core is broken.
This models are formally verified against Spike. I f their behavior is incorrect then so is the behavior of spike. And spike is the golden reference implementation.
from riscv-formal.
Hi Clifford,
C.LI with rd=0 and the other documented hint instructions certainly shouldn't be decoded by any core as illegal instructions, but would it not be better to distinguish them in riscv-formal as distinct instructions from C.li, C.lui, etc., for testing? Given the spec says they must either act as no-ops or have a defined hint implementation, but must never modify architectural state, conceptually it seems wrong to define them as having an architectural effect. Of course in practice having rd=0 should mean that the instructions do nothing and are equivalent to no-ops, but not distinguishing the hint instructions might potentially lead to insidious bugs - perhaps an x0 register in a software emulator which incorrectly can be written to, but would still pass these tests? It seems a concerning precedent to just ignore the hint instructions. Outside of riscv-formal I've found this has led to issues in other tools, such as disassemblers incorrectly decoding them as either compressed instructions or illegal instructions, and I can imagine a developer assuming that they could use riscv-formal's instruction definitions as references for developing their own tool.
I've been testing various RISC-V implementations for (inadvertent) undocumented instructions recently, so these kind of bugs slipping through verification have been on my mind. Would be interested to hear your thoughts on this - thanks!
from riscv-formal.
C.LI with rd=0 and the other documented hint instructions certainly shouldn't be decoded by any core as illegal instructions, but would it not be better to distinguish them in riscv-formal as distinct instructions from C.li, C.lui, etc., for testing?
That would be possible, but I don't see it adding anything. All hint instructions already are NOPs when interpreted as regular instruction, and that's exactly what all cores do, at least until actual hint instructions are standardized.
There are no additional properties to assert for hint instructions. So what would we gain?
Given the spec says they must either act as no-ops or have a defined hint implementation, but must never modify architectural state
And that's exactly the semantic you get from riscv-formal.
Last time I checked spike is also doing the same thing.
are equivalent to no-ops, but not distinguishing the hint instructions might potentially lead to insidious bugs - perhaps an x0 register in a software emulator which incorrectly can be written to, but would still pass these tests?
Writing anything that isn't 0 to x0 would be identified as bug by riscv-formal. And that has nothing to do with hint instructions at all. It's the same if you have uncompressed instructions that are effectively NOPs.
from riscv-formal.
Related Issues (20)
- Adding support for a newRISC-V processor to riscv-formal HOT 4
- Failed Checks in picorv32 Verification Following Quickstart Guide HOT 3
- Misaligned JAL(R) RD register writeback expectations HOT 4
- JAL handling procedure HOT 1
- Value of rs1 during CSR*I instructions HOT 2
- OOPS forget i said anything
- Incorrect width of insn_funct6 in I-type (shift variation) instruction format?
- Debug modelling
- "ERROR: syntax error, unexpected TOK_RAND" in quick start guide HOT 2
- Instruction checks: non-universal assertions should be generated based on instruction type
- How to set values in the genchecks.cfg file?
- Support for Zce?
- When is rvfi_halt supposed to be used?
- rvfi_reg_check is possibly broken (picorv32 also fails the assertion) HOT 3
- Can WARL read-only be handled in csrw_check?
- are rvfi_valid and rvfi_trap mutually exclusive.
- Some confusion about skip option
- Is this repo no longer active?
- syntax error in quickstart HOT 1
- RV32I and RV64I
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from riscv-formal.